Low power pulse triggered D-flip flops using MTCMOS and Self-controllable voltage level circuit

Author

Parakundil, Liaqat Moideen ; Saraswathi, N.

Author_Institution

Electron. & Commun. Eng., SRM Univ., Chennai, India

fYear

2014

fDate

8-10 May 2014

Firstpage

517

Lastpage

521

Abstract

Reducing power consumption is a crucial task for any circuits. Increased demand for portable devices with reduced power dissipation has put necessary traction to design low power circuits. Both explicit and implicit pulse triggered flip flops are designed. Multiple Threshold CMOS (MTCMOS) technique and Self-controllable voltage level (SVL) circuit are employed to reduce power consumption. All the circuits are designed in 45nm technology for 1 GHz frequency.

Keywords

CMOS integrated circuits; flip-flops; low-power electronics; power consumption; MTCMOS technique; SVL circuit; explicit pulse triggered flip flops; frequency 1 GHz; implicit pulse triggered flip flops; low power circuits; multiple threshold CMOS technique; portable devices; power consumption; self-controllable voltage level circuit; size 45 nm; Clocks; Computers; Conferences; Discharges (electric); Power demand; Transistors; Voltage control; Clocked Pair Shared Flip Flop (CPSFF); Conditional Data Mapping Flip Flop (CDMFF); Conditional Discharge Flip Flop (CDFF); MTCMOS; SVL;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4799-3913-8

Type

conf

DOI

10.1109/ICACCCT.2014.7019139

Filename

7019139