Low power area optimized novel architecture for Software Defined Radio in FPGA

Field Programmable Gated Array (FPGA) provides a way for developing system on chip reconfigurable modules with high performance. In this paper, FPGA architecture for recovering audio signals from digitally modulated frequency wave is proposed, which would be a starting point for developing an efficient Software Defined Radio (SDR) architecture. At the modulator and demodulator sections, a Digital Frequency Generator (DFG) is used for generating the carrier wave by exploiting the quarter wave symmetry of sine or cosine waves with dynamic range of more than 90dB. Digital Phase Locked Loop (DPLL) with DFG is used to demodulate the Frequency Modulated (FM)audio signals. Simulation and synthesis are done using Xilinx 13.1. The proposed architecture works around a frequency of 106MHz and uses 1.032 K equivalent gates when tested using XC3S1600E-4fg320, Spartan 3E board with power consumption of around 120mW.