Scan test data volume reduction in multi-clocked designs with safe capture technique

As a result of increasing design size and complexity, the multiple clock domain design style has become a new trend in the industry. Several techniques to test circuits with multiple clocks are known; however, they often result in increased test time and tester memory for large and complex circuits. This paper presents a strategy to reduce the test pattern count during ATPG by forcing a safe capture behavior when multiple clocks are applied during capture. The usage of multiple clocks allows additional observability, which can significantly reduce the pattern count for circuits with many clocks. Experimental results indicate that proposed strategy results in larger and moreover, more consistent reduction in test sizes.