A low power Schmitt Trigger design using SBT technique in 180nm CMOS technology

Author

Suresh, A.

Author_Institution

Sch. of VLSI Design & Embedded Syst., Nat. Inst. of Technol., Kurukshetra, India

fYear

2014

fDate

8-10 May 2014

Firstpage

533

Lastpage

536

Abstract

This paper presents the effect of source voltage and load capacitance on the performance of CMOS Schmitt Trigger circuit with self-bias transistor (SBT) technique which was used to reduce power. The CMOS Schmitt Trigger circuit was modified by designing the transistors aspect ratio on the basis of conventional CMOS Schmitt Trigger and it is implemented using CADENCE Virtuoso in Spectra Simulator using UMC-180nm technology for different modified design. Results are compared in terms of propagation delay, power, and energy-delay product. From the simulation results, the modified CMOS Schmitt Trigger was able to operate between 0.8V to 1.5V voltage range.

Keywords

CMOS digital integrated circuits; integrated circuit design; low-power electronics; transistor circuits; trigger circuits; CADENCE Virtuoso; CMOS Schmitt trigger circuit; CMOS technology; SBT technique; Spectra Simulator; UMC technology; energy-delay product; load capacitance; low power Schmitt trigger design; propagation delay; self-bias transistor technique; size 180 nm; source voltage; voltage 0.8 V to 1.5 V; CMOS integrated circuits; Capacitance; Propagation delay; Switching circuits; Threshold voltage; Transistors; Trigger circuits; Schmitt trigger; aspect ratio; hysteresis; leakage reduction; low power; propagation delay;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on

Conference_Location

Ramanathapuram

Print_ISBN

978-1-4799-3913-8

Type

conf

DOI

10.1109/ICACCCT.2014.7019142

Filename

7019142