Title :
A variable drivability (VD) output buffer for the system in a package (SIP) and high frequency wafer test
Author :
Tomishima, Shigeki ; Tanizaki, Hiroaki ; Niiro, Mitsutaka ; Maruta, Masanao ; Hidaka, Hideto ; Tada, T. ; Gamo, Kenji
Author_Institution :
ULSI Dev. Center, Mitsubishi Electr. Corp., Itami, Japan
Abstract :
A system in a package (SIP) is another candidate of future embedded system chips against the system on a chip (SOC). The SIP has intra connections, which have a small I/O load. On the other hand, the high frequency wafer test has a large I/O load caused by the probe, Hi-Fix and coaxial cable. This paper makes these incompatible load problems clear and proposes a new output buffer to overcome them. A new variable drivability (VD) output buffer can provide the optimum driving ability for both the SIP intra-connection and the high frequency (over 100 MHz) wafer test. This proposed output buffer realizes a new SIP test flow containing a high frequency wafer test and a reduction of the total test cost of embedded DRAM chips by 35% compared with the SOC test cost.
Keywords :
DRAM chips; buffer circuits; circuit simulation; coaxial cables; embedded systems; integrated circuit design; integrated circuit economics; integrated circuit testing; logic design; logic simulation; logic testing; probes; system-on-chip; 100 MHz; Hi-Fix; SIP test flow; SOC; coaxial cables; embedded DRAM chips; embedded system chips; high frequency wafer test; large probe I/O load; optimum driving ability VD output buffers; small I/O load SIP intra connections; system in a package test; system on a chip; total test cost reduction; variable drivability output buffers; Costs; Design engineering; Electronic equipment testing; Embedded system; Frequency conversion; Logic testing; Packaging; Random access memory; System testing; System-on-a-chip;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041758
