A persistent diagnostic technique for unstable defects

Author

Sato, Yasuo ; Yamazaki, Lwao ; Yamanaka, Hiroki ; Ikeda, Toshio ; Takakura, Masahiro

Author_Institution

Device Dev. Center, Hitachi Ltd., Tokyo, Japan

fYear

2002

fDate

2002

Firstpage

242

Lastpage

249

Abstract

We present a persistent diagnostic technique for unstable defects, such as open defects or delay defects. A new "segment model" diagnosis for the completely open defects is discussed. Here, we not only focus on the behavior of the principal offender, but also the behavior of the accomplices which cause the unstable behavior of the defect. In this paper, a technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed. Some experimental results of actual chips are shown.

Keywords

automatic test equipment; circuit stability; delays; failure analysis; fault diagnosis; integrated circuit layout; integrated circuit modelling; integrated circuit testing; logic testing; completely open defects; delay defects; delay fault testing method; layout information; open defects; open fault diagnosis; persistent diagnostic technique; segment model diagnosis; unstable defect behavior causes; unstable defects; Crosstalk; Data mining; Delay; Dictionaries; Fault diagnosis; Logic testing; System testing; Temperature; Threshold voltage; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041766

Filename

1041766