Embedded memory test and repair: infrastructure IP for SOC yield

Today´s system-on-chip typically embeds memory IP cores with very large aggregate bit count per SoC. This trend requires using dedicated resources to increase memory yield, while containing test and repair cost and minimizing time-to-volume. This paper summarizes the evolution of such yield optimization resources, compares their trade-offs, and concentrates on on-chip infrastructure IP. To maximize the repair efficiency, this infrastructure IP needs to leverage the memory design knowledge and the process failure data. The ideal solution is to integrate the memory IP and its infrastructure IP into a single composite IP that yields itself effectively.