Title :
An integrated approach to yield loss characterization
Author :
Craig, Mark ; Jee, Alvin ; Maniar, Prashant
Author_Institution :
Test Chip Div., HPL, Inc, Austin, TX, USA
Abstract :
Presents an integrated approach for achieving improved yield ramp and enhanced manufacturing margins for deep sub-micron process technologies. This methodology highlights the combination of design IP for process technology characterization, tailored data reduction and analysis of the design components for data characterization, and fault modeling and extraction for root cause failure determination. This approach enables semiconductor companies to characterize yield loss and improve manufacturing process.
Keywords :
VLSI; fault simulation; integrated circuit testing; integrated circuit yield; production testing; system-on-chip; data characterization; deep sub-micron process technologies; design components; fault modeling; manufacturing margins; manufacturing process; process technology characterization; root cause failure determination; tailored data reduction; yield loss characterization; yield ramp; Circuit faults; Circuit testing; Data analysis; Failure analysis; Foundries; Information analysis; Manufacturing processes; Optimized production technology; Process design; Vehicles;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041778
