A method for the optimization of a CMOS driven, center tap terminated (CTT) network in a shared bus design

Author

Cericola, Fred J. ; Bhattacharyya, Bidyut K.

Author_Institution

Assembly Technol. Dev., Intel Corp., Chandler, AZ, USA

fYear

1994

fDate

1-4 May 1994

Firstpage

676

Lastpage

682

Abstract

In this paper, a theoretical method is described for the optimization of a CMOS driven, center tap terminated network. This method is verified by circuit simulations. In the simulations, we have assumed a 70 ohm characteristic impedance of the board interconnects and at the same time, n number of various loads connected at different points on that line. Each of these loads has some stub length that can vary from 1.0 inch to 1.5 inch depending on the packaging technology. The above example is a shared bus situation. This method will also work on other topologies as long as the effective characteristic impedance of that topology is less than Zmin, where Zmin is the minimum characteristic impedance that the CMOS driver can support for a given noise criteria

Keywords

CMOS integrated circuits; circuit analysis computing; circuit optimisation; driver circuits; integrated circuit interconnections; integrated circuit noise; integrated circuit packaging; printed circuit layout; 1.0 to 1.5 in; 70 ohm; CMOS driven network; board interconnects; center tap terminated network; circuit simulations; effective characteristic impedance; minimum characteristic impedance; noise criteria; packaging technology; shared bus design; stub length; Bonding; CMOS technology; Circuit simulation; Impedance; Integrated circuit interconnections; Intelligent networks; Optimization methods; Packaging; Resistors; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference, 1994. Proceedings., 44th

Conference_Location

Washington, DC

Print_ISBN

0-7803-0914-6

Type

conf

DOI

10.1109/ECTC.1994.367598

Filename

367598