Title :
Test methodology for Motorola´s high performance e500 core based on PowerPC instruction set architecture
Author :
Bailey, B. ; Metayer, A. ; Svrcek, B. ; Tendolkar, N. ; Wolf, E. ; Fiene, E. ; Alexander, M. ; Woltenberg, R. ; Raina, R.
Author_Institution :
Somerset Design Center, Motorola Inc., Austin, TX, USA
Abstract :
This paper presents the DFT techniques used in Motorola\´s high performance e500 core, which implements the PowerPC "Book E" architecture and is designed to run at 600 MHz to 1 GHz. Highlights of the DFT features are at-speed logic built-in self-test (LBIST) for delay fault detection, very high test coverage for scan based at-speed deterministic delay-fault test patterns, 100% BIST for embedded memory arrays and 99.2 % stuck-at fault test coverage for deterministic scan test patterns. A salient design feature is the isolation ring that facilitates testing of the core when it is integrated in an SoC or host processor.
Keywords :
automatic test pattern generation; boundary scan testing; built-in self test; delays; design for testability; high-speed integrated circuits; instruction sets; integrated circuit testing; logic testing; microprocessor chips; system-on-chip; 600 MHz to 1 GHz; DFT techniques; Motorola e500 core; PowerPC Book E architecture; PowerPC instruction set architecture; SoC; at-speed deterministic test patterns; at-speed logic BIST; delay fault detection; delay-fault test patterns; deterministic scan test patterns; embedded memory arrays; high test coverage; host processor; isolation ring; logic built-in self-test; microprocessor core; scan based test patterns; stuck-at fault test coverage; test methodology; Automatic testing; Books; Built-in self-test; Delay; Design for testability; Frequency; Logic arrays; Logic design; Logic testing; Microprocessors;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041808
