Title :
Support for debugging in the Alpha 21364 microprocessor
Abstract :
The Alpha 21364 microprocessor consists of 153 million transistors operating at 1.2 GHz. The chip includes essentially all of the logic that previous generations relegated to hundreds of support ASICs, including a large L2 cache, memory controllers and a router. While this integration delivers outstanding performance and reliability, the consequent reduction of visibility in the base design posed significant challenges for debug. This paper describes architectural changes made in anticipation of these challenges, and their effect on the debug of this complex, leading edge design.
Keywords :
boundary scan testing; built-in self test; cache storage; computer architecture; computer debugging; design for testability; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic analysers; logic testing; microprocessor chips; 1.2 GHz; Alpha 21364 microprocessor debug support; BIST/BISR logic; JTAG boundary scan; L2 caches; base design visibility reduction; debugging; design for testability; memory controllers; microprocessor architecture; microprocessor operating frequency; on-chip logic analyzers; reliability; routers; support ASIC; visibility ports; Amplitude shift keying; Computer bugs; Debugging; Hardware; Instruments; Logic testing; Memory management; Microprocessors; Operating systems; Silicon;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041809
