Title :
FPGA test and coverage
Author :
Toutounchi, Shahin ; Lai, Andrew
Abstract :
This paper presents an FPGA test and coverage methodology. BIST and "shift register" styles of test are discussed. Gate level fault grading results are then presented. Use of an "iterative logic unit" and its impact on test and fault grading is discussed.
Keywords :
built-in self test; fault diagnosis; field programmable gate arrays; integrated circuit testing; logic testing; network routing; BIST; FPGA test methodology; Xilinx Virtex-II architecture; configurable logic blocks; dedicated routing; fault modeling; gate level fault grading; hierarchical routing resources; iterative logic unit; programmable interconnect point; shift register styles; test coverage methodology; Application specific integrated circuits; CMOS technology; Circuit faults; Circuit testing; Field programmable gate arrays; Logic design; Logic testing; Shift registers; Software tools; Transceivers;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041811
