Title :
Fault grading FPGA interconnect test configurations
Author :
Tahoori, Mehdi Baradaran ; Mitra, Subhasish ; Toutounchi, Shahin ; McCluskey, Edward J.
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
Conventional fault simulation techniques for FPGAs are very complicated and time consuming. The other alternative, FPGA fault emulation technique, is incomplete, and can be used only after the FPGA chip is manufactured. In this paper, we present efficient algorithms for computing the fault coverage of a given FPGA test configuration. The faults considered are opens and shorts in FPGA interconnects. Compared to conventional methods, our technique is orders of magnitude faster, while is able to report all detectable and undetectable faults.
Keywords :
fault diagnosis; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic testing; FPGA interconnect test configurations; Virtex architecture; fault coverage; fault grading; interconnect fault model; interconnect opens; interconnect shorts; Automatic testing; Circuit faults; Circuit testing; Emulation; Field programmable gate arrays; Integrated circuit interconnections; Manufacturing; Programmable logic arrays; Routing; Switches;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041812
