Development of a fail-safe microprocessor LSI with self-diagnosis mechanism depending on an M-sequence code signature

Author

Takahashi, Sei ; Taira, Munehisa ; Saegusa, Hidetaka ; Hoshino, Takehiko ; Nakamura, Hideo

Author_Institution

Coll. of Sci. & Technol., Nihon Univ., Chiba, Japan

fYear

2001

fDate

2001

Firstpage

191

Lastpage

195

Abstract

A bus-level synchronized computer system is widely utilized in the field of railway signaling in Japan. It may be recognized that there is a problem of disadvantage in manufacturing cost reduction. We intend to integrate a bus-level synchronized FS (fail-safe) computer into an LSI chip, in expectation of cost reduction and performance enhancement. An economical FS one-chip computer utilizing system LSI technology is realized. It assures fail-safety by means of a novel fault diagnosis mechanism depending on an M-sequence code signature. These techniques are reported in detail

Keywords

fault diagnosis; fault tolerant computing; large scale integration; microprocessor chips; railways; signalling; Japan; LSI chip; LSI technology; M-sequence code signature; bus-level synchronized FS computer; bus-level synchronized computer system; cost reduction; economical FS one-chip computer; fail-safe computer; fail-safe microprocessor LSI; fail-safety; fault diagnosis mechanism; manufacturing cost reduction; performance enhancement; railway signaling; self-diagnosis mechanism; Circuits; Computer architecture; Computer errors; Control systems; Costs; Hardware; Large scale integration; Microprocessors; Rail transportation; Software safety;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable Computing, 2001. Proceedings. 2001 Pacific Rim International Symposium on

Conference_Location

Seoul

Print_ISBN

0-7695-1414-6

Type

conf

DOI

10.1109/PRDC.2001.992697

Filename

992697