• DocumentCode
    2377865
  • Title

    KGD levels and effects

  • Author

    Rates, Jim

  • Author_Institution
    Chip Supply Inc., Orlando, FL, USA
  • fYear
    1994
  • fDate
    1-4 May 1994
  • Firstpage
    617
  • Abstract
    Summary form only given, as follows. This paper presents the authors definition of Known Good Die, and discusses various KGD processes and associated yields. Die quality versus first time module assembly yield, and die reliability versus module failures in time (FIT) are also discussed. The author also examines KGD processing costs and tradeoffs to module costs
  • Keywords
    circuit optimisation; failure analysis; integrated circuit reliability; integrated circuit yield; microassembling; multichip modules; KGD levels; MCMs; die quality; die reliability; failures in time; known good die; module assembly yield; module failures; processing costs; yields; Assembly; Costs; Integrated circuit reliability; Integrated circuit yield; Manufacturing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 1994. Proceedings., 44th
  • Conference_Location
    Washington, DC
  • Print_ISBN
    0-7803-0914-6
  • Type

    conf

  • DOI
    10.1109/ECTC.1994.367610
  • Filename
    367610
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2377865