Title :
Screening minVDD outliers using feed-forward voltage testing
Author :
Madge, R. ; Goh, B.H. ; Rajagopalan, V. ; Macchietto, C. ; Daasch, R. ; Schuermyer, C. ; Taylor, C. ; Turner, David
Author_Institution :
LSI Logic Corp., Gresham, OR, USA
Abstract :
MinVDD testing using full vector set search routines consumes too much test time. A 3-step process is proposed using: (1) a reduced vector set (RVS) binary search to measure the intrinsic (defect free) minVDD for a die; (2) a feed-forward to the full vector set (FVS) for low voltage testing; and (3) delta VDD and nearest neighbor residual statistical post-processing (SPP) are applied to the data to screen the minVDD outliers that are identified using the RVS binary search. RVS vs. FVS correlation data is shown on 3 products. Data shows minVDD yield fallout of 0.2-0.8% and 20% of the minVDD outliers shows significant VDD shifts in burn-in.
Keywords :
boundary scan testing; built-in self test; failure analysis; feedforward; integrated circuit reliability; integrated circuit testing; integrated circuit yield; logic testing; statistical analysis; BIST; FVS; RVS; RVS/FVS correlation data; SPP; VDD burn-in shifts; delta VDD; failure analysis; feed-forward full vector set low voltage testing; feed-forward voltage testing; full vector set search routines; intrinsic/defect free minVDD die measurements; minVDD outlier screening; minVDD testing; minVDD yield fallout; nearest neighbor residual statistical post-processing; reduced vector set binary search; scan testing; test time; Costs; Feedforward systems; Integrated circuit testing; Laboratories; Large scale integration; Logic design; Logic testing; Low voltage; Nearest neighbor searches; Production;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041819
