Title :
A high-speed capacitance extraction algorithm for multi-level VLSI interconnects
Author :
Le Coz, Yannick L. ; Iverson, Ralph B.
Author_Institution :
Center for Integrated Electron., Rensselaer Polytech. Inst., Troy, NY, USA
Abstract :
The authors present preliminary results of a novel stochastic algorithm for high-speed capacitance extraction in multi-level VLSI interconnects. The algorithm is related to a statistical procedure for solving Laplace´s equation known as a floating random-walk method. Benchmark calculations for three-dimensional cross-wire geometries were performed on a MAC IIfx personal computer, operating at 0.3 MFLOPS. Execution times were typically 40 s for an accuracy of less that 5%. Overall computational efficiency stems from various factors: suitability to rectilinear geometries, statistical-error cancellation, selective integration over Gaussian surfaces, and direct capacitance-matrix evaluation
Keywords :
VLSI; capacitance measurement; electronic engineering computing; integrated circuit technology; metallisation; Gaussian surfaces; Laplace´s equation; MAC IIfx personal computer; benchmark calculations; capacitance-matrix evaluation; computational efficiency; floating random-walk method; high-speed capacitance extraction algorithm; multilevel VLSI interconnects; rectilinear geometries; selective integration; statistical-error cancellation; stochastic algorithm; three-dimensional cross-wire geometries; Capacitance; Computational geometry; Dielectrics; Electric potential; Electrodes; Integral equations; Integrated circuit interconnections; Laplace equations; Stochastic processes; Very large scale integration;
Conference_Titel :
VLSI Multilevel Interconnection Conference, 1991, Proceedings., Eighth International IEEE
Conference_Location :
Santa Clara, CA
Print_ISBN :
0-87942-673-X
DOI :
10.1109/VMIC.1991.153026
