DocumentCode :
2377928
Title :
Wafer-level defect-based testing using enhanced voltage stress and statistical test data evaluation
Author :
Quach, Minh ; Pham, Tuan ; Figal, Tim ; Kopitzke, Bob ; O´Neill, Peggy
Author_Institution :
Agilent Labs., Agilent Technol. Co., Fort Collins, CO, USA
fYear :
2002
fDate :
2002
Firstpage :
683
Lastpage :
692
Abstract :
In this paper, we illustrate the effectiveness of wafer-level enhanced voltage stress (EVS) along with low voltage sweep (LVS), IDDQ and other parametric tests to screen early life failure defects. Our experiment shows temporary undetected defects after repeated exposure to certain applied voltages. We demonstrate a statistical methodology to screen die with suspected early life failure defects.
Keywords :
failure analysis; fault location; integrated circuit reliability; integrated circuit testing; integrated circuit yield; statistical analysis; EVS; LVS; early life failure defect screening; early life reliability failures; enhanced voltage stress testing; low voltage sweep tests; parametric tests; repeated applied voltage exposure; statistical analysis; statistical die screening methodology; statistical test data evaluation; temporary undetected defects; wafer-level defect-based testing; yield defect density; Application specific integrated circuits; Companies; Costs; Dynamic voltage scaling; Fabrication; Laboratories; Life testing; Low voltage; Statistical analysis; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2002. Proceedings. International
ISSN :
1089-3539
Print_ISBN :
0-7803-7542-4
Type :
conf
DOI :
10.1109/TEST.2002.1041820
Filename :
1041820
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2377928
بازگشت