Automatic scan insertion and test generation for asynchronous circuits

Author

Beest, Frank Te ; Peeters, Ad ; Verra, Marc ; Van Berkel, Kees ; Kerkhoff, Hans

Author_Institution

MESA+ Res. Inst., Twente Univ., Enschede, Netherlands

fYear

2002

fDate

2002

Firstpage

804

Lastpage

813

Abstract

A test method for asynchronous handshake circuits is presented that is based on synchronous full-scan techniques. The method adds a synchronous test mode to the circuit, in which the entire circuit is controlled by external clocks. This enables the use of conventional test generation tools. The method resulted in an operational flow, capable of automatically testing any handshake circuit with test-quality equal to synchronous circuits. Several circuits have been evaluated, demonstrating over 99% stuck-at fault coverage.

Keywords

asynchronous circuits; automatic test pattern generation; clocks; fault diagnosis; integrated circuit testing; integrated logic circuits; logic testing; asynchronous handshake circuits; automatic scan insertion; automatic test generation; automatic testing; external clock controlled circuit; operational flow; stuck-at fault coverage; synchronous full-scan techniques; synchronous test mode; test generation tools; test method; test quality; Asynchronous circuits; Automatic testing; Circuit faults; Circuit testing; Design methodology; Laboratories; Libraries; Logic circuits; Logic testing; Tellurium;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041834

Filename

1041834