An ATPG for threshold testing: obtaining acceptable yield in future processes

When VLSI scaling reaches closer to the limits of laws of physics and to the limits of fabrication processes, yields will decrease, especially at desired speed. However, for a large class of applications, chips need not be perfect to be acceptable. In this paper, we describe the notion of threshold testing that can help improve effective yield for future processes. We then develop an ATPG and demonstrate that significant increase in effective yield can be attained at negligible increase in test application cost.