Generation of low power dissipation and high fault coverage patterns for scan-based BIST

This paper presents a low hardware overhead test pattern generator (TPG) for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable length of test sequence. Since the correlation between consecutive vectors applied to a circuit during BIST is significantly lower, switching activity in the circuit can be significantly higher during BIST than that during its normal operation. Excessive switching activity during test application can damage CUTs during BIST. The proposed BIST decreases the number of transitions that occur at scan inputs during scan shift operations and hence decreases switching activity during BIST. The proposed BIST is comprised of two TPGs: LT-RTPG and 3-weight WRBIST TPG, both of which are proposed in previous publications. This paper shows that the 3-weight WRBIST TPG, which is used to detect random pattern resistant faults, can also be used to reduce switching activity in CUTs during BIST. Experimental results also show that the proposed BIST can be implemented with very low area overhead.