A new test generation approach for embedded analogue cores in SoC

Author

Stancic, M. ; Fang, L. ; Weusthof, M.H.H. ; Tijink, R.M.W. ; Kerkhoff, H.G.

Author_Institution

MESA Res. Inst., Twente Univ., Enschede, Netherlands

fYear

2002

fDate

2002

Firstpage

861

Lastpage

869

Abstract

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.

Keywords

automatic test pattern generation; design for testability; feedback; integrated circuit testing; mixed analogue-digital integrated circuits; system-on-chip; DFT solutions; PID feedback-based test signal backtrace; SoC cores; embedded analogue cores; fast tolerance-box propagation algorithm; mixed-signal SoC testing; multifrequency test pattern generation method; test-generation approach; testability-analysis based ATPG method; Analytical models; Application software; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Fault detection; Signal generators; System testing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2002. Proceedings. International

ISSN

1089-3539

Print_ISBN

0-7803-7542-4

Type

conf

DOI

10.1109/TEST.2002.1041840

Filename

1041840