A new test generation approach for embedded analogue cores in SoC

This paper proposes a new test-generation approach for embedded analogue cores in SoC. The key features of this approach are the developed testability-analysis based multifrequency test pattern generation method, the novel PID feedback-based test signal backtrace procedure and the fast tolerance-box propagation algorithm. Moreover, possible DFT solutions are discussed. Finally, this approach has been validated by experiments conducted on a real hardware implementation.