Test setup simulation - a high-performance VHDL-based virtual test solution meeting industrial requirements

Virtual test (VT) allows the debug of mixed-signal test programs and associated test hardware in a simulation environment if (1) a cheap, fast and sufficiently accurate chip model, and (2) a converter software linking test programs to simulators can be made available. This paper presents TSS (test setup simulation), a high-performance VT solution based on pure VHDL modeling of the hardware involved, a VHDL-based virtual tester concept and a snapshot test data extractor linking the test program to a simulator together with VT results for a complex telecom device.