On identifying indistinguishable path delay faults and improving diagnosis

Work in path delay fault testing and fault simulation has gained importance in the industry since supplementing stuck-at fault coverage with delay fault coverage may result in better defect coverage than that is possible with stuck-at fault coverage alone. Timing related failures must be diagnosed to determine which nodes or paths in the circuit have excessive delays and techniques are needed to simplify the process of attributing the delays to a minimal set of nodes or paths. In this work, we propose a method for determining path delay faults that are tested simultaneously by the same test and do not have separate tests either because of circuit functionality or restrictions imposed by a given test set. We call such faults indistinguishable path delay faults. We further propose a method for identifying scanout nodes in the circuit that reduce the number of indistinguishable faults and improve diagnostic resolution. The method for identifying indistinguishable faults can be used before test application to determine the extent of diagnostic resolution possible for a given test set. It also enables a designer to make the design changes needed for improving diagnostic resolution. This has a large impact on the turnaround time for the diagnosis and debug processes. We perform experiments on the partitions of a picoJava™ processor core to show the effectiveness of the proposed method. Results show that it requires only a reasonable amount of time for identifying indistinguishable faults and that the proposed methods are practical for deployment in an industrial environment.