Title :
Hierarchical simulation of high speed digital interconnects using a packaging simulator
Author :
Base, Mark S. ; Steer, Michael B. ; Franzon, Paul D.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
A hierarchical strategy is presented which permits the tradeoff of modeling and simulation accuracy with simulation speed in the simulation of high speed signals on interconnects in multichip modules and printed circuit boards. Using a point modeling paradigm for discontinuities and impulse response thresholding a smooth transition is achieved between delay modeling and full circuit simulation
Keywords :
circuit analysis computing; delays; digital simulation; integrated circuit interconnections; multichip modules; printed circuit design; printed circuit layout; delay modeling; discontinuities; full circuit simulation; hierarchical strategy; high speed digital interconnects; high speed signals; impulse response thresholding; multichip modules; packaging simulator; point modeling paradigm; printed circuit boards; simulation speed; Circuit simulation; Computational modeling; Computer simulation; Delay effects; Distributed parameter circuits; Frequency; Integrated circuit interconnections; Multichip modules; Printed circuits; Semiconductor device packaging;
Conference_Titel :
Electronic Components and Technology Conference, 1994. Proceedings., 44th
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-0914-6
DOI :
10.1109/ECTC.1994.367647
