Title :
Incremental diagnosis of multiple open-interconnects
Author :
Liu, Brandon J. ; Veneris, Andreas ; Takahashi, Hiroshi
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
With increasing chip interconnect distances, open-interconnect is becoming an important defect. The main challenge with open-interconnects stems from its non-deterministic real-life behavior In this work, we present an efficient diagnostic technique for multiple open-interconnects. The algorithm proceeds in two phases. During the first phase, potential solution sets are identified following a model-free incremental diagnosis methodology. Heuristics are devised to speed up this step and screen the solution space efficiently. In the second phase, a generalized fault simulation scheme enumerates all possible faulty behaviors for each solution from the first phase. We conduct experiments on combinational and full-scan sequential circuits with one, two and three open faults. The results are very encouraging.
Keywords :
CMOS logic circuits; circuit simulation; combinational circuits; fault diagnosis; fault simulation; integrated circuit interconnections; integrated circuit modelling; logic simulation; sequential circuits; CMOS; chip interconnect distances; combinational circuits; fault simulation scheme; faulty behaviors; full-scan sequential circuits; heuristics; incremental diagnosis; logic level; model-free incremental diagnosis methodology; multiple open-interconnects; nondeterministic real-life behavior; open faults; solution sets; Circuit faults; Circuit testing; Fault diagnosis; Feedback; Iterative algorithms; Logic testing; Manufacturing processes; Roads; Thermal stresses; Wires;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041865