Signal integrity loss in SoC´s interconnects: a diagnosis approach using embedded microprocessor

Presents a systematic approach for utilizing the microprocessor capabilities in testing the SoC´s interconnects for signal integrity. We propose a graph representation of SoC/interconnects to minimize the test time while performing thorough test of interconnects for integrity loss. This is achieved by using the embedded microprocessor for two main tasks: (1) to dynamically determine the best test plan based on resource constraints and the test results from previous sessions, and (2) to execute the test plan, that includes test generation/delivery, signature analysis/diagnosis and process control.