DocumentCode :
2378854
Title :
Neighbor selection for variance reduction in IDDQ and other parametric data
Author :
Daasch, Robert W. ; Cota, Kevin ; McNames, James ; Madge, Robert
Author_Institution :
Dept. of Electr. & Comput. Eng., Portland State Univ., OR, USA
fYear :
2002
fDate :
2002
Firstpage :
1240
Lastpage :
1248
Abstract :
The subject of this paper is variance reduction and nearest neighbor residual estimates for IDDQ and other continuous-valued test measurements. The key, new concept introduced is data-driven neighborhood identification about a die to reduce the variance of good and faulty IDDQ distributions. Using LSI Logic production data, neighborhood selection techniques are demonstrated. The main contribution of the paper is variance reduction by the systematic use of the die location and wafer- or lot-level patterns and improved identification of die outliers of continuous-valued test data such as IDDQ.
Keywords :
data analysis; integrated circuit testing; integrated circuit yield; leakage currents; production testing; statistical analysis; 0.18 micron; IDDQ data; IDDQ distributions; LSI Logic production data; continuous-valued test measurements; data-driven neighborhood identification; die location; die outliers; leakage current; lot-level patterns; nearest neighbor residual estimates; neighborhood selection techniques; parametric data; variance reduction; wafer-level patterns; yield dependence; Data engineering; Design engineering; Equations; Integrated circuit testing; Laboratories; Large scale integration; Logic design; Logic testing; Nearest neighbor searches; Production;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2002. Proceedings. International
ISSN :
1089-3539
Print_ISBN :
0-7803-7542-4
Type :
conf
DOI :
10.1109/TEST.2002.1041882
Filename :
1041882
Link To Document :
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