DocumentCode
2378995
Title
Position statement: TAPs all over my chips
Author
Oakland, Steven E.
Author_Institution
IBM Microeletronics Div., Essex Junction, VT, USA
fYear
2002
fDate
2002
Firstpage
1192
Abstract
Summary form only given. An increasing number of system-on-chip (SoC) application-specific integrated circuits (ASICs) have more than one embedded processor with a test access port (TAP). A processor´s TAP facilitates a hardware interface to a software development/debug tool. The author presents a technique whereby embedded TAPs can be accessed one at a time via a single TAP consisting of four or five pins. No TAP selection pins are required, and the runtime performance of debug software is relatively independent of the number of embedded processors.
Keywords
automatic testing; boundary scan testing; integrated circuit testing; system-on-chip; IEEE Standard 1149.1compliance; SoC ASICs; application-specific integrated circuits; chip-level TAP; embedded TAPs; embedded processors; hardware interface; software development/debug tool; system-on-chip; test access port; Application specific integrated circuits; Circuit testing; Embedded software; Hardware; Integrated circuit testing; Pins; Programming; Runtime; System testing; System-on-a-chip;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2002. Proceedings. International
ISSN
1089-3539
Print_ISBN
0-7803-7542-4
Type
conf
DOI
10.1109/TEST.2002.1041899
Filename
1041899
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