Author :
Waldron, Niamh ; Wang, Gang ; Nguyen, Ngoc Duy ; Orzali, Tommaso ; Merckling, Clement ; Brammertz, Guy ; Ong, Patrick ; Winderickx, Gillis ; Hellings, Geert ; Eneman, Geert ; Caymax, Matty ; Meuris, Marc ; Horiguchi, Naoto ; Thean, Aaron
Abstract :
In this paper we present results from an InGaAs/InP implant free quantum well device integrated fully in a Si CMOS processing line. The virtual InP substrates are generated using a Si template which is prepared by standard STI processing. The Si in the STI trenches is etched and a Ge seed layer grown.
Keywords :
CMOS integrated circuits; III-V semiconductors; electron mobility; elemental semiconductors; etching; gallium arsenide; indium compounds; integration; ion implantation; quantum well devices; semiconductor growth; silicon; III-V semiconductors; InGaAs-InP; Si; etching; free quantum well device; high-mobility CMOS; implant; integration; seed layer grown; CMOS integrated circuits; Indium gallium arsenide; Indium phosphide; Logic gates; Silicon; Substrates; Surface treatment;
