Safe clocking register assignment in datapath synthesis

For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. While the timing violation due to the fail of the setup constraint can be fixed by tuning a clock frequency or using a delayed latch, the timing violation due to the fail of the hold constraint cannot be fixed by those methods in general. Our approach to delay variations (in particular, the hold constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by contra-data-direction (CDD) clocking. After the formulation of this new register assignment problem, we prove NP-hardness of the problem, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by CDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits.