Mixed-signal BIST: fact or fiction

Summary form only given. Embedded test is essential for many of today´s high-speed electronic designs that involve state-of-the-art silicon processes. Attempting to perform timing and frequency measurements across the chip I/O is fraught with parasitic interconnect issues, leading to excessive noise pick-up, asymmetrical delays and uneven incident/reflection levels. Interestingly enough, the problem of on-chip interconnects is a well-recognized problem in many VLSI-related conferences. Packing such large numbers of interconnects in such a small volume leads to numerous coupling and cross-talk phenomena that are limiting the performance of advanced circuit designs. The problem associated with moving large volumes of data across the chip interface during the test phase seems to have gained less interest at leading conferences when in fact the problem is quite similar, if not worse. As the number of chip I/Os increase, the separation distance and conductor thickness is being forced to decrease, leaving only the length and material properties of the interconnect under our control. Changing the material properties of the interconnect is a steady endeavor and will less likely result in any radical improvement, leaving us with only the length of the interconnect under our direct control. At the present time, the tester-DUT interconnect length is on the order of 10 cm-100 cm, limiting the interconnect bandwidth to, at most, a few GHz. To measure signals with bandwidths beyond this limit, the tester electronics MUST be brought closer to the DUT, or even better, directly on-chip. Hence, BIST or some other form of embedded test will be a fact, it just a matter of time.