Title :
Multi Gigahertz digital test challenges and techniques
Author_Institution :
Dept. of Electr. & Comput. Eng., Waterloo, Ont., Canada
Abstract :
The clock frequency of high performance VLSIs has exceeded 2 GHz. Over the years, aggressive scaling of CMOS process technology has resulted in a 30% annual performance improvement for digital circuits. However, tester speed has improved by only 12% every year. This paper discusses various test methodologies being used to cope with this speed disparity. These include: very low voltage test techniques; DFT structure incorporation; low frequency test modes; and dynamic CMOS implementations with integrated test mode structures.
Keywords :
CMOS digital integrated circuits; automatic test equipment; design for testability; integrated circuit testing; logic testing; very high speed integrated circuits; 2 GHz; ATE performance; CMOS process technology scaling; DFT structure incorporation; digital circuit performance improvement; dynamic CMOS implementations; high performance VLSI clock frequency; integrated test mode structures; low frequency test modes; multi-GHz digital IC test challenges/techniques; tester speed; very high speed IC; very low voltage test techniques; CMOS logic circuits; CMOS technology; Circuit faults; Circuit testing; Clocks; Delay; Digital circuits; Frequency; Logic testing; Semiconductor device testing;
Conference_Titel :
Test Conference, 2002. Proceedings. International
Print_ISBN :
0-7803-7542-4
DOI :
10.1109/TEST.2002.1041932
