Pervasive multi Giga bit links - an ATE challenge?

The data rates of high-speed serial communications have increased to the point where many communications designers are implementing multilane serializer/deserializer I/O architectures on their highly complex SOCs. Taking such an approach maximizes the use of limited pins on these devices while enabling ultra high bandwidths at data rates beyond 2.5 Gbits/second for highspeed communications protocols. A review of test methodologies to deal with these challenges is required. The leading theme for manufacturing needs to be: where do we need to rely on external judgement (ATE), where can DFT/BIST be best used and how do we compliment the solution space at best?.