DocumentCode
2379796
Title
An improved micro-architecture for function approximation using piecewise quadratic interpolation
Author
Erez, Shai ; Even, Guy
Author_Institution
Sch. of Electr. Eng., Tel-Aviv Univ., Tel-Aviv
fYear
2008
fDate
12-15 Oct. 2008
Firstpage
422
Lastpage
426
Abstract
We present a new micro-architecture for evaluating functions based on piecewise quadratic interpolation. The micro-architecture consists mainly of a look-up table and two multiply-accumulate units. Previous micro-architectures based on piecewise quadratic interpolation have been shown to be efficient for small precision (e.g., single precision) computations. Moreover, they are as fast as piecewise linear interpolation while requiring smaller tables. Our main contribution is in circumventing the need for the additional squaring unit that appears in previous micro-architectures. Based on the proposed micro-architecture, we present a detailed design of single precision reciprocal approximation (1/x). Our design is based on two multiply-accumulate units that contain truncated Booth radix 4 multipliers. The number of partial products in this design is reduced by over 20% compared to previous designs using quadratic interpolation. The latency of this design is roughly the delay of 19 full-adder gates, and it can be easily pipelined into two stages each with a delay of 10 full-adder gates.
Keywords
approximation theory; interpolation; microprocessor chips; function approximation; look-up table; microarchitecture; piecewise linear interpolation; piecewise quadratic interpolation; Clocks; Delay; Function approximation; Interpolation; Logic; Piecewise linear approximation; Piecewise linear techniques; Polynomials; Product design; Table lookup;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design, 2008. ICCD 2008. IEEE International Conference on
Conference_Location
Lake Tahoe, CA
ISSN
1063-6404
Print_ISBN
978-1-4244-2657-7
Electronic_ISBN
1063-6404
Type
conf
DOI
10.1109/ICCD.2008.4751895
Filename
4751895
Link To Document