A 1.5 V 86 mW/ch 8-channel 622-3125 Mb/s/ch CMOS SerDes macrocell with selectable mux/demux ratio

Author

Yang, F. ; O´Neill, J. ; Larsson, P. ; Inglis, D. ; Othmer, J.

Author_Institution

Agere Syst., Holmdel, NJ, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

68

Abstract

An 8-channel serial link transceiver realizes 20 Gb/s full duplex total I/O throughput with <700 mW dissipation from a 1.5 V supply and occupies 2 mm/sup 2/ in 0.16 /spl mu/m CMOS. An analog DLL allows tracking of frequency offset up to 400 ppm. The receiver, employing an integrate-and-dump front-end, achieves 30 mVpp sensitivity.

Keywords

CMOS logic circuits; delay lock loops; demultiplexing; integrated circuit interconnections; integrated circuit measurement; integrating circuits; multiplexing; transceivers; 0.16 micron; 1.5 V; 20 Gbit/s; 622 to 3125 Mbit/s; 700 mW; 86 mW; CMOS SerDes macrocell; analog DLL; frequency offset tracking; full duplex total I/O throughput; integrate-and-dump front-end receiver; power dissipation; selectable mux/demux ratio; sensitivity; serial link transceiver; Circuits; Clocks; Detectors; Macrocell networks; Multiplexing; Phase detection; Power supplies; Throughput; Transceivers; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992942

Filename

992942