Title :
A quad 3.125 Gb/s/channel transceiver with analog phase rotators
Author :
Dong Zheng ; Xuecheng Jin ; Cheung, E. ; Rana, M. ; Ge Song ; Yong Jiang ; Sutu, Y.-H. ; Bin Wu
Author_Institution :
BitBlitz Commun., Fremont, CA, USA
Abstract :
A 0.18 /spl mu/m/sup 2/ CMOS quad transceiver provides 12.5 Gb/s full-duplex raw data throughput at 200 mW/channel consumption. An analog phase rotator in CDR (clock/data recovery) eliminates the quantization error of digital phase interpolation techniques, resulting in <17 ps peak-peak output jitter.
Keywords :
CMOS integrated circuits; analogue processing circuits; integrated circuit design; integrated circuit interconnections; interpolation; jitter; phase changing circuits; quantisation (signal); synchronisation; transceivers; CDR; CMOS quad transceiver; analog phase rotators; channel power consumption; clock/data recovery; digital phase interpolation techniques; full-duplex raw data throughput; peak-peak output jitter; quantization error; Built-in self-test; Clocks; Detectors; Energy consumption; Frequency; Jitter; Optical fiber communication; Transceivers; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992943
