A dynamic accuracy-refinement approach to timing-driven technology mapping

Technology mapping aims at searching an optimal implementation for a Boolean netlist using gates from a technology library. Compared with its NP-complete area minimization counterpart, DAG mapping for delay minimization is considered much sophisticated because matching choices must be made without knowing actual arrival times and output loads. Traditional approaches to this problem involve too many approximate simplifications, and are far from accurate. In contrast, this paper tackles this problem directly under load-dependent DAG mapping. The enabling techniques for accurate optimization include on-the-fly load-estimation refinement, breadth-first backward covering for load consolidation, and use of a piecewise linear model for accurate timing calculation. Experimental results show that, compared with the state-of-the-art mapper, our method averagely reduces circuit delay by 39%, with 11% increase in area, for large benchmark circuits.