Title :
A 0.2-2 GHz 12 mW multiplying DLL for low-jitter clock synthesis in highly-integrated data communication chips
Author :
Farjad-Rad, R. ; Dally, W. ; Hoik-Tiaq Ng ; Poulton, John ; Stone, T. ; Rathi, Rahul ; Lee, Edward ; Huang, Dijiang ; Nathan, Ralph
Author_Institution :
Velio Commun. Inc., Milpitas, CA, USA
Abstract :
The MDLL, in 0.18 /spl mu/m CMOS, has 0.05 mm/sup 2/ active area and 200 MHz to 2 GHz speed range. The complete synthesizer, including the output clock buffers, dissipates 12 mW from a 1.8 V supply at 2.0 GHz. This MDLL architecture is used as a clock multiplier in a highly-integrated chip, and has jitter of 1.73 ps (rms) and 15.6 ps (pk-pk) at 2 GHz.
Keywords :
clocks; data communication equipment; delay lock loops; multiplying circuits; pulse generators; timing jitter; 0.18 micron; 0.2 to 2 GHz; 1.8 V; 12 mW; MDLL; active area; clock multiplier; data communication chips; low-jitter clock synthesis; multiplying DLL; output clock buffers; Circuit noise; Clocks; Delay; Frequency; Jitter; Logic; Phase locked loops; Ring oscillators; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992946
