Title :
Is there always performance overhead for regular fabric?
Author :
Yi-Wei Lin ; Marek-Sadowska, M. ; Maly, W. ; Pfitzner, A. ; Kasprowicz, D.
Abstract :
In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.
Keywords :
field effect transistor circuits; integrated circuit interconnections; integrated circuit layout; integrated circuit manufacture; photolithography; proximity effect (lithography); 3-D geometry transistor; OPC-free interconnect manufacturing process; VeSFET; chip manufacturability; high-density transistor arrays; integrated circuit fabrication; optical proximity correction; photo-lithographiy; power density; super-regular layout style; vertical slit field effect transistor circuits; CMOS technology; Capacitance; FETs; Fabrics; Geometry; Integrated circuit interconnections; Libraries; MOSFETs; Manufacturing processes; Timing;
Conference_Titel :
Computer Design, 2008. ICCD 2008. IEEE International Conference on
Conference_Location :
Lake Tahoe, CA
Print_ISBN :
978-1-4244-2657-7
DOI :
10.1109/ICCD.2008.4751916
