Title :
Tuning the Germanium TFET: Device Optimization for Maximum Ion
Author :
Hähnel, D. ; Fischer, I. ; Isemann, H. ; Oehme, M. ; Schulze, J.
Author_Institution :
Inst. of Semicond. Eng., Univ. of Stuttgart, Stuttgart, Germany
Abstract :
As MOSFET scaling has attained the 22 nm node, alternative concepts are intensively being investigated. The concept of the Tunneling Field Effect Transistor (TFET) is currently being explored as one of the device concepts most likely to enable energy efficient computation that, in addition, can potentially outperform the conventional MOSFET. Attaining the necessary Ion (International Technology Roadmap for Semiconductors) (ITRS) 2011, 1,367 μA/μm, High-performance (HP) table Process Integration, Devices, and Structures (PIDS) 545 μA/μm, Low Operating Power Performance (LOP) table PIDS and 374 μA/μm Low Standby Power (LSTP) table PIDS is at present one of the major obstacles on the road towards establishing the TFET as a serious alternative to the MOSFET.
Keywords :
MOSFET; germanium; tunnelling; Ge; HP table PIDS; ITRS; International Technology Roadmap for Semiconductors; LOP table; LSTP table; MOSFET scaling; TFET tuning; energy efficient computation; high-performance table process integration devices and structure; low operating power performance table; low standby power table; optimization; size 22 nm; tunneling field effect transistor tuning; Heterojunctions; Logic gates; MOSFET circuits; Molecular beam epitaxial growth; Silicon; Solids; Tunneling;
Conference_Titel :
Silicon-Germanium Technology and Device Meeting (ISTDM), 2012 International
Conference_Location :
Berkeley, CA
Print_ISBN :
978-1-4577-1864-9
Electronic_ISBN :
978-1-4577-1863-2
DOI :
10.1109/ISTDM.2012.6222483
