Gate oxide damage and charging characterization in a 0.13 μm, triple oxide (1.7/2.2/5.2nm) bulk technology

Author

Hook, Terence B. ; Harmon, David ; Lai, Wing

Author_Institution

IBM Microeletronics, Essex Junction, VT, USA

fYear

2002

fDate

2002

Firstpage

10

Lastpage

13

Abstract

The authors present data from a 0.13 μm technology, in which the thickest oxide is 5.2 nm and the thinnest 1.7 nm, with a 2.2 nm oxide provided simultaneously. Our results indicate that dielectric integrity is affected for the 2.2 nm oxide, threshold voltage shift is important only for the 5.2 nm oxide, but that the 1.7 nm oxide is virtually immune to charging damage by any measure applied here (threshold voltage, gate leakage, TDDB, SILC). Qualitatively similar results are obtained for NFETs and PFETs.

Keywords

MOS integrated circuits; MOSFET; dielectric thin films; electric breakdown; etching; integrated circuit interconnections; ion implantation; isolation technology; leakage currents; masks; oxidation; semiconductor device breakdown; silicon compounds; 0.13 μm technology node; 0.13 micron; 1.7 nm; 2.2 nm; 5.2 nm; FET; N implantation; NFET; SILC; SiO₂; TDDB; dielectric integrity; gate definition; gate leakage; gate oxide charging; gate oxide damage; interconnect technology; masking; oxidation; shallow trench isolation; sidewall spacer technology; stress-induced leakage current; subtractive wet etch; threshold voltage shift; time-dependent dielectric breakdown; triple oxide (1.7/2.2/5.2nm) bulk technology; Antenna measurements; Dielectric measurements; FETs; Gate leakage; Insulation; Microelectronics; Nitrogen; Oxidation; Testing; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Plasma- and Process-Induced Damage, 2002 7th International Symposium on

Print_ISBN

0-9651577-7-6

Type

conf

DOI

10.1109/PPID.2002.1042597

Filename

1042597