Removing hazards in multi-level logic optimization for generalized fundamental-mode asynchronous circuits

Unlike traditional synthesis methods for fundamental-mode asynchronous circuits which require dedicated hazard-free algorithms, a multi-level logic optimization algorithm is developed to take advantage of the powerful and mature synchronous synthesis algorithms and technology libraries. The proposed algorithm is based on a hazard analysis method, which not only detects any hazard in an arbitrary circuit structure, but also identifies the cause of the hazard. Then, a hazard removal process is performed on the circuit synthesized using synchronous algorithms to generate a hazard-free circuit. The proposed synthesis algorithm achieves high efficiency by exploiting synchronous optimization algorithms and technology libraries, as demonstrated through the experimental results.