DocumentCode
2380338
Title
New parallel programming techniques for hardware design
Author
Singh, Satnam
Author_Institution
Microsoft Research, 77 JJ Thomson Ave, Cambridge CB3 0FB, United Kingdom
fYear
2007
fDate
15-17 Oct. 2007
Firstpage
163
Lastpage
167
Abstract
We present some recent advances in concurrent and parallel programming which are promising condidates for the design and specific of hardware and in particular reconfigurable systems. We explore the relationship between parallel programming and hardware design and ask the question “are these two activities the same thing at an important level of abstraction”? In particular, we consider join patterns from join calculus, software transactional memory, futures and nested data parallel programming.
Keywords
Calculus; Computational modeling; Computer architecture; Concurrent computing; Field programmable gate arrays; Hardware; Parallel programming; Programming profession; Silicon; Supercomputers;
fLanguage
English
Publisher
ieee
Conference_Titel
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location
Atlanta, GA, USA
Print_ISBN
978-1-4244-1710-0
Electronic_ISBN
978-1-4244-1710-0
Type
conf
DOI
10.1109/VLSISOC.2007.4402491
Filename
4402491
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