The hazard-free superscalar pipeline fast fourier transform algorithm and architecture

This paper examines the superscalar pipeline Fast Fourier Transform algorithm and architecture. The algorithm presents a memory management scheme to prevent memory contention throughout the pipeline stages. The fundamental algorithm, a switch-based FFT pipeline architecture and an example 64-point FFT pipeline are presented. The proposed superscalar architecture substantially improves the FFT processing. The pipeline consists of log2N stages, where N is number of FFT points. Each stage can have M Processing Elements (PEs.) As a result, the architecture speed up is M*log2N. The pipeline algorithm is configurable to any M ≫ 1.