Title :
IIR digital filter for delta-sigma decimation, channel selection, and square-root raised-cosine nyquist filtering
Author :
Mirabbasi, S. ; Martin, K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A 1.8 V 0.18 /spl mu/m CMOS /spl Delta//spl Sigma/ decimation filter also performs channel-selection and an approximate root-raised-cosine Nyquist pulse-shaping. The 0.1 mm/sup 2/ IIR structure consumes 6.4 mW (26.8 mW) at 64 MHz (240 MHz) oversampling frequency.
Keywords :
CMOS integrated circuits; IIR filters; broadband networks; channel allocation; delta-sigma modulation; digital filters; modulators; pulse shaping circuits; 0.18 /spl mu/m CMOS; 0.18 micron; 1.8 V; 240 MHz; 240 MHz oversampling frequency; 6.4 mW; IIR digital filter; broadband communication; channel selection; delta-sigma decimation filter; infinite impulse-response filter; root-raised-cosine Nyquist filter; Bandwidth; Baseband; Digital filters; Equalizers; Filtering; IIR filters; Noise shaping; Quantization; Sampling methods; Signal resolution;
Conference_Titel :
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-7335-9
DOI :
10.1109/ISSCC.2002.992970
