DocumentCode
2380546
Title
A self-regulating VCO with supply sensitivity of <0.15%-delay/1%-supply
Author
In Chul Hwang ; Sung-Mo Kang
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Volume
1
fYear
2002
fDate
7-7 Feb. 2002
Firstpage
140
Abstract
A self-regulating VCO has supply sensitivity <0.15%-delay/1%-supply. The design uses a differential delay cell that contains an nMOS transmission gate for delay adjustment and a built-in feedback circuit for power-supply rejection. The charge-pump PLL embedded with this VCO has 40 ps peak-to-peak jitter at 450 MHz output with VCO at 900 MHz.
Keywords
circuit feedback; delay circuits; phase locked loops; timing jitter; voltage-controlled oscillators; 450 MHz; 900 MHz; built-in feedback circuit; charge pump PLL; differential delay cell; nMOS transmission gate; peak-to-peak jitter; power supply rejection; self-regulating VCO; supply sensitivity; Circuits; Clocks; Delay effects; Flip-flops; Latches; Phase noise; Tail; Transceivers; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International
Conference_Location
San Francisco, CA, USA
Print_ISBN
0-7803-7335-9
Type
conf
DOI
10.1109/ISSCC.2002.992975
Filename
992975
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