Title :
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC
Author :
Sudhakar, M. ; Kamala, R.V. ; Srinivas, M.B.
Author_Institution :
Center for VLSI and Embedded Systems Technologies (CVEST), International Institute of Information Technology (IIIT) - Hyderabad, Gachibowli, Hyderabad - 500032, Andhra Pradesh, INDIA
Abstract :
This paper presents a reconfigurable, bit-sliced, scalable Montgomery multiplier architecture which can operate in both prime and binary fields, that is, GF(p) and GF(2n). It can be configured for any bit length thus making it applicable for emerging elliptic curve cryptography (ECC) as well as widely used RSA cryptosystems. Existing word-based, scalable multiplier architectures perform well for key sizes in RSA (but not ECC) as they result in higher computational time. Limited utility of word-based architectures for ECC precisions, which are in general not equal to an integer multiple of word-size, is discussed and a new bit-sliced architecture to improve the performance in terms of delay is proposed. The new bit-sliced, scalable architecture computes the Montgomery multiplication with fewer clock cycles compared to existing architectures by configuring them at bit-level rather than at word-level, without compromising on the performance. Synthesis results (Mentor Graphic’s Leonardo Spectrum) are compared with that of other scalable architectures and discussed.
Keywords :
Clocks; Computer architecture; Delay; Doped fiber amplifiers; Elliptic curve cryptography; High performance computing; Performance gain; Registers; Size control; Very large scale integration;
Conference_Titel :
Very Large Scale Integration, 2007. VLSI - SoC 2007. IFIP International Conference on
Conference_Location :
Atlanta, GA, USA
Print_ISBN :
978-1-4244-1710-0
Electronic_ISBN :
978-1-4244-1710-0
DOI :
10.1109/VLSISOC.2007.4402507