An Investigation of Growth and Properties of Si Capping Layers Used in Advanced SiGe/Ge Based pMOS Transistors

A continuous scaling of CMOS devices urges investigation of alternative to standard planar transistor device architectures. One of the ways to increase pFETs performance is to incorporate high mobility SiGe or ultimately strained-Ge channels. Apart from a higher mobility, Ge based channels also offer a beneficial Vt shift allowing a simplified way of CMOS Gate First integration as well as improved NBTI performance when Si-cap is used. This Si layer is needed in order to avoid a non- controlled SiGe oxidation, causing an increase of interface defects (Dit) during high-K gate fabrication starting with a thin wet chemical oxide. In this work, we are reporting two approaches for deposition of selective Si Cap layers. In the first instance, a sequence of not selective Si growth via silane-based process with a following poly Si etching step by HCl is used. The second approach involves a two step Si Cap growth using dichlorosilane and temperature ramp up. We compare both approaches with a non selective silane-based process by means of Secondary Ion Mass Spectroscopy followed by electrical characterisation of buried channel and implant free quantum well pMOS devices in which mentioned above not selective and selective processes were used.