A low-power RISC microprocessor using dual PLLs in a 0.13 /spl mu/m SOI technology with copper interconnect and low-k BEOL dielectric

Author

Geissler, S. ; Appenzeller, D. ; Cohen, E. ; Charlebois, S. ; Kartschoke, P. ; McCormick, P. ; Rohrer, N. ; Salem, G. ; Sandon, P. ; Singer, B. ; Von Reyn, T. ; Zimmerman, J.

Author_Institution

Microelectron. Div., IBM Corp., Essex Junction, VT, USA

Volume

1

fYear

2002

fDate

7-7 Feb. 2002

Firstpage

148

Abstract

Microprocessors achieving clock frequencies >1 GHz for mobile applications require solutions to maintain long battery life. Circuit and architecture solutions for dynamic frequency switching between multiple PLLs, DC power reduction methods, and impact of low-k dielectric on timing and power are discussed.

Keywords

CMOS digital integrated circuits; dielectric thin films; digital phase locked loops; integrated circuit interconnections; low-power electronics; microprocessor chips; reduced instruction set computing; silicon-on-insulator; timing; 0.13 micron; DC power reduction methods; RISC microprocessor; SOI technology; Si; clock frequencies; copper interconnect; dual PLLs; dynamic frequency switching; low-k BEOL dielectric; low-power electronics; timing; CMOS technology; Clocks; Copper; Delay; Diodes; Frequency; Logic; Microprocessors; Phase locked loops; Reduced instruction set computing;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2002. Digest of Technical Papers. ISSCC. 2002 IEEE International

Conference_Location

San Francisco, CA, USA

Print_ISBN

0-7803-7335-9

Type

conf

DOI

10.1109/ISSCC.2002.992979

Filename

992979